Half Bridge Cell

Description of the Half Bridge Cell converter in Schematic Editor.

Component Not Supported: This component is not currently supported in TyphoonSim. Adding this component to your model will prevent you from being able to run your model in TyphoonSim. Please disable or remove this component from your model before attempting to run your model in TyphoonSim mode.
Figure 1. Component Icon

Solver platform

The Half Bridge Cell converter can be simulated using two different solver platforms:
  • UltraCore: Default option, which utilizes UltraCore to simulate the converter with enhanced resolution, using UltraCore step. UltraCore weight of the component is 1.
  • SPC: Simulates the converter using SPC resources, with a simulation timestep equal to the rest of the electrical model. SPC weight of the component is 1.
When the switching frequency is higher than 100 kHz, the usage of UltraCore is advised. If UltraCore is selected as the solver platform, the component will contain an interfacing electrical circuit towards the rest of the circuit, as described in Electrical circuit interface.

The Half Bridge Cell component in the Typhoon HIL Schematic Editor Library uses the current source interface. The interface is formulated in such a way that the voltages are inputs to the dedicated UltraCore, while the currents are its outputs. Figure 2 shows the circuit interface of the Half Bridge Cell component.

Figure 2. Circuit interface of Half Bridge Cell component

Schematic Block Diagram

A schematic block diagram of the Half Bridge Cell with corresponding switch naming is given in Figure 3. Inductance L and its serial resistance R are integrated in Half Bridge Cell the component in order to have the converter structure that can be simulated in the UltraCore.

Figure 3. A schematic block diagram of the Half Bridge Cell

Control

Selecting Digital inputs as the Control parameter enables assigning gate drive inputs to any of the digital input pins (from 1 to 32(64)). For example, if S1 is assigned to 1, the digital input pin 1 will be routed to the S1 switch gate drive. In addition, the gate_logic parameter selects either active high (High-level input voltage VIH turns on the switch), or active low (Low-level input voltage VIL turns on the switch) gate drive logic, depending on the design of the external controller. In TyphoonSim, digital signals are read from the internal virtual IO bus. Hence, if some signal is sent to digital ouput 1, it will appear on digital input 1.

Selecting Internal modulator as the Control parameter, enables use of the internal PWM modulator for driving S1 and S2 switches instead of digital input pins. In this configuration, two additional component inputs will be present. The En input is used to enable/disable the internal PWM modulator, while In is used as a reference signal input.

Analog output variable naming for the Half Bridge Cell switching block (internal to the component)

Analog output variable name Description
i_L Inductance current

Digital Alias

If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.

Ports

  • In+ (electrical)
    • DC input + port
  • In- (electrical)
    • DC input - port
  • Out+ (electrical)
    • DC output + port
  • Out- (electrical)
    • DC output - port
  • En (in)
    • Available if Internal modulator control is selected
    • Used to enable/disable internal modulator
  • In (in)
    • Available if Internal modulator control is selected
    • Used to specify modulation signal value for internal modulator
  • Freq (in)
    • Available if Internal modulator control is selected and Variable carrier frequency is selected as the modulator's operation mode
    • Used to specify modulator's carrier frequency
  • Offset (in)
    • Available if Internal modulator control is selected and Variable carrier phase offset is selected as the modulator's operation mode
    • Used to specify modulator's carrier offset

General (Tab)

  • Control
    • Specifies how switches are controlled. It is possible to choose between: Digital inputs or Internal modulator
    • More details about each type of control can be found in the Control section
  • If Digital inputs is selected as Control, the following properties can be used:
    • S1
      • Digital input that is used to control S1 switch
    • S1_logic
      • Logic that will be applied to control signal for S1
      • Active high or active low
    • S2
      • Digital input that is used to control S2 switch
    • S2_logic
      • Logic that will be applied to control signal for S2
      • Active high or active low
  • Gate control enabling
    • If enabled, gives a possibility to control if changes in the gate control signal are applied or not
  • Sen
    • Available if Gate control enabling is enabled
    • Digital input that enables/disables switching
  • Sen_logic
    • Available if Gate control enabling is enabled
    • Logic that will be applied to Sen signal
  • If Internal modulator is selected as Control, the following properties can be used:
    • Operation mode
      • Specifies the source of the internal modulator carrier frequency
      • If Operation mode is Fixed carrier frequency, then the frequency can be specified on the component properties
      • If Operation mode is Variable carrier frequency, then the frequency can be specified using a signal processing port
    • Carrier frequency (Hz)
      • Available if the Operation mode is a Fixed carrier frequency
      • Specifies the internal modulator's carrier frequency
    • Phase operation mode (deg)
      • Specifies the source of the internal modulator carrier frequency
      • If Operation mode is Fixed carrier phase offset, then the carrier phase offset can be specified on the component properties
      • If Operation mode is Variable phase offset, then the carrier phase offset can be specified using a signal processing port
    • Carrier phase offset (Hz)
      • Available if the Phase operation mode is a Fixed carrier phase offset
      • Specifies the internal modulator's carrier phase offset
    • Dead time period
      • Specifies dead time for the internal modulator in seconds
    • Reference signal [min, max]
      • This property is set by default to [0.0, 1.0]
      • Specifies carrier signal minimal and maximal value
      • Vector containing two values: the minimal carrier signal value, followed by the maximal carrier signal value

Electrical (Tab)

  • L
    • Output inductance
  • R
    • Inductor series resistance. Switch Rds(on) can be included in this parameter.

Solver (Tab)

  • Solver platform
    • Select on which platform the converter block will be simulated: SPC or UltraCore

Advanced (Tab)

The Advanced tab is available only when solver platform is SPC.

  • Oversampling setting
    • With this property, you can select which GDS oversampling algorithm will be used in the component. There are two options: Global GDS oversampling and Switch-level GDS oversampling. More information about these algorithms can be found in the dedicated documentation pages. Switch-level GDS oversampling is suitable for applications which use a high switching frequency and where more than one GDS transition can happen during one simulation step.
      Note: If Switch-level GDS oversampling is enabled in a component that supports it, Global GDS oversampling will be ignored for all components in the same sub-circuit.
      Feature Ignored: GDS oversampling is a technique that is specifically used in real-time simulation to ensure high fidelity simulation. It is not needed in TyphoonSim simulation because the variable step solver can process any switching event exactly at the time when it occurs. Changing the Oversampling setting value will not affect TyphoonSim simulation at all.

Extras (Tab)

  • Short-circuit resistance
    • Available only when UltraCore is selected as Solver platform.
    • If converter is short-circuited, the current that converter draws is limited by this resistance.
  • Enhance light-load stability
    • Available only when UltraCore is selected as Solver platform.
    • This option should be enabled if the converter is expected to operate in CCM under light load. In such an environment, this option will ensure the stable, appropriately damped response. Output inductor (simulated by UltraCore) and output capacitor (simulated outside of UltraCore) exhibit a resonant response damped by two resistances: series resistance of the inductor and load resistance. Simulation of this resonant circuit is split between the two computational units executed in parallel which exchange the state variables, meaning that it behaves similarly to a system discretized using Forward Euler discretization, i.e., it can yield an unstable response if it is very lightly damped. When this option is enabled, the additional damping is introduced during the model discretization, which ensures the numerical stability during transients when the converter is in light-load or no-load operation. During steady-state operation, additional losses will not be introduced.
  • Output capacitance
    • Available only when UltraCore is selected as Solver platform.
    • Visible if Enhance light-load stability is enabled.
    • Capacitance of the capacitor connected to the converter output. This value is only used to enhance the light-load stability. The capacitor must still be connected externally and will be simulated outside of UltraCore.
    • If multiple parallel cells are used, the output capacitor shall be divided by the number of cells in parallel.
Signal visibility is calculated based on the 'signal_access' property and whether or not a parent component in its hierarchy is locked or not. Components that are not contained within locked components expose their signals regardless of the 'signal_access' property. The 'signal_access' property can have one of three values:
  • Public - Components marked as public expose their signals on all levels.
  • Protected - Components marked as protected will hide their signals to components outside of their first locked parent component.
  • Inherit - Components marked as inherit will take the nearest parent 'signal_access' property value that is set to a value other than inherit.