Active Clamp Forward-Flyback

Description of the Active Clamp Forward-Flyback converter in Schematic Editor.

Figure 1. Component Icon
Note: When SPC is used as the Solver platform, Switch-level GDS oversampling is used for this converter block in order to optimize model execution for high switching frequencies. Due to this, SPC solver settings with this converter block can only be used with firmware configurations that support Switch-level GDS oversampling. Global GDS oversampling is not currently supported when simulating this converter block on SPC.

Solver platform

The Active Clamp Forward-Flyback converter can be simulated using two different solver platforms:
  • UltraCore: Default option, which utilizes UltraCore to simulate the converter with enhanced resolution, using UltraCore step.
  • SPC: Simulates the converter using SPC resources, with a simulation timestep equal to the rest of the electrical model.

When the switching frequency is higher than 100 kHz, the usage of UltraCore is advised.

If UltraCore is selected as the solver platform, the component will contain an interfacing electrical circuit towards the rest of the circuit, as described in Electrical circuit interface. The Active Clamp Forward-Flyback component in the Typhoon HIL Schematic Editor Library uses the current source interface. The interface is formulated in such a way that the voltages are inputs to the dedicated UltraCore, while the currents are its outputs. Figure 2 shows the circuit interface of the Active Clamp Forward-Flyback comoponent.

Figure 2. Circuit interface of Active Clamp Forward-Flyback component

Schematic Block Diagram

The schematic block diagram of the Active Clamp Forward-Flyback converter component differs depending on selected Solver platform. When UltraCore is used, a clamping capacitor is placed inside the converter block. This is done due to the existence of fast dynamics between transformer inductances and the clamping capacitor, which is important to consider for real-time simulations. By simulating these fast dynamics using UltraCore, model fidelity is improved. In TyphoonSim, Solver platform affects only the internal structure of the component. Schematic block diagrams with corresponding switch naming when either the UltraCore or SPC platform is used are given in Figure 3 and Figure 4, respectively.

If SPC is selected as Solver platform, the weight of the Active Clamp Forward-Flyback converter is 2.

Figure 3. A schematic block diagram of the Active Clamp Forward-Flyback converter component with corresponding switch naming - Solver platform: UltraCore
Figure 4. A schematic block diagram of the Active Clamp Forward-Flyback converter component with corresponding switch naming - Solver platform: SPC

Control

Selecting Digital inputs as the Control parameter enables assigning gate drive inputs to any of the digital input pins (from 1 to 32(64)). For example, if S1 is assigned to 1, the digital input pin 1 will be routed to the S1 switch gate drive. In addition, the gate_logic parameter selects either active high (High-level input voltage VIH turns on the switch), or active low (Low-level input voltage VIL turns on the switch) gate drive logic, depending on the design of the external controller. In TyphoonSim, digital signals are read from the internal virtual IO bus. Hence, if some signal is sent to digital ouput 1, it will appear on digital input 1.

Selecting Internal modulator as the Control parameter, enables use of the internal PWM modulator for driving S1 and S2 switches instead of digital input pins. In this configuration, two additional component inputs will be present. The En input is used to enable/disable the internal PWM modulator, while In is used as a reference signal input.

Selecting Model as the Control parameter, enables setting of the switch gate drive signals directly from the signal processing model. The input pin gates appears on the component. It is a 2-element vector input, where the first value (index 0) controls the S1 gate and the second value (index 1) controls the S2 gate. When controlled from the model, logic is always active high. This control option is available only when SPC is selected as Solver platform.

Analog output variable naming for the active clamp forward-flyback switching block (internal to the component)

Analog output variable name Description
L1 Current of primary side leakage inductance
Lm1 Current of magnetizing inductance of the top transformer
Lm2 Current of magnetizing inductance of the bottom transformer
iD1 Current of D1 diode. Present only when UltraCore is used.
iD2 Current of D2 diode. Present only when UltraCore is used.
i_clamp Clamping capacitor input current. Present only when UltraCore is used.
v_C_clamp Clamping capacitor voltage. Present only when UltraCore is used.

Digital Alias

If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.

Ports

  • IN+ (electrical)
    • DC input + port
  • IN- (electrical)
    • DC input - port
  • C+ (electrical)
    • Positive port of the clamp capacitor. Exists if solver platform is SPC
  • OUT+ (electrical)
    • DC output + port
  • OUT- (electrical)
    • DC output - port
  • s_ctrl (in)
    • Available if model control is selected
    • 2-element (scalar) input gate signal for switches
  • En (in)
    • Available if Internal modulator control is selected
    • Used to enable/disable internal modulator
  • In (in)
    • Available if Internal modulator control is selected
    • Used to specify modulation signal value for internal modulator
  • Freq (in)
    • Available if Internal modulator control is selected and Variable carrier frequency is selected as the modulator's operation mode
    • Used to specify modulator's carrier frequency

General (Tab)

  • Control
    • Specifies how switches are controled. It is possible to choose between: Digital inputs, Internal modulator, and Model
    • More details about each type of control can be found in the Control section
  • If Digital inputs is selected as Control, the following properties can be used:
    • S1
      • Digital input that is used to control S1 switch
    • S1_logic
      • Logic that will be applied to control signal for S1
      • Active high or active low
    • S2
      • Digital input that is used to control S2 switch
    • S2_logic
      • Logic that will be applied to control signal for S2
      • Active high or active low
    • Gate control enabling
      • If enabled, gives a possibility to control if changes in the gate control signal are applied or not
    • Sen
      • Available if Gate control enabling is enabled
      • Digital input that enables/disables switching
    • Sen_logic
      • Available if Gate control enabling is enabled
      • Logic that will be applied to Sen signal
  • If Model is selected as Control, the following properties can be used:
    • Execution rate
      • Defines the period between two updates of gate signals for the component. Gate signals are provided as a signal processing input to component
  • If Internal modulator is selected as Control, the following properties can be used:
    • Operation mode
      • Specifies the source of the internal modulator carrier frequency
      • If Operation mode is Fixed carrier frequency, then the frequency can be specified on the component properties
      • If Operation mode is Variable carrier frequency, then the frequency can be specified using a signal processing port
    • Carrier frequency (Hz)
      • Available if the Operation mode is a Fixed carrier frequency
      • Specifies the internal modulator's carrier frequency
    • Dead time period
      • Specifies dead time for the internal modulator in seconds
    • Reference signal [min, max]
      • This property is set by default to [0.0, 1.0]
      • Specifies carrier signal minimal and maximal value
      • Vector containing two values: the minimal carrier signal value, followed by the maximal carrier signal value
    • Load mode
      • Specifies on which event the new value of the modulation signal will be applied in the internal modulator
        • If on min is selected, new value will be applied when carrier reaches minimal value
        • If on max is selected, new value will be applied when carrier reaches maximal value
        • If on either is selected, new value will be applied when carrier reaches minimal or maximal value

Transformer (Tab)

  • n1
    • Number of turns of primary winding
  • n2
    • Number of turns of secondary winding
  • L1
    • Leakage inductance of primary
  • Lm
    • Magnetization inductance
  • R1
    • Primary resistance
  • R2
    • Secondary resistance
  • Rm
    • Equivalent resistance modeling the iron core losses

Solver (Tab)

  • Solver platform
    • Select on which platform the converter block will be simulated: SPC or UltraCore

Extras (Tab)

The Extras tab gives you the opportunity to set Signal Access Management for the component.
Signal visibility is calculated based on the 'signal_access' property and whether or not a parent component in its hierarchy is locked or not. Components that are not contained within locked components expose their signals regardless of the 'signal_access' property. The 'signal_access' property can have one of three values:
  • Public - Components marked as public expose their signals on all levels.
  • Protected - Components marked as protected will hide their signals to components outside of their first locked parent component.
  • Inherit - Components marked as inherit will take the nearest parent 'signal_access' property value that is set to a value other than inherit.