Three phase two level current source inverter

This section describes three phase two level current source inverter

A block diagram and input parameters for a three phase current inverter block are given in Table 1.

Table 1. A three-phase two level current source inverter block in the HIL Toolbox
component component dialog window component parameters

Three phase current source inverter

  • General
    • Control source (Digital inputs, Model)
    • Phase A S1 (1..32)
    • Phase A S2(1..32)
    • Phase B S1 (1..32)
    • Phase B S2 (1..32)
    • Phase C S1 (1..32)
    • Phase C S2 (1..32)
    • gate_logic (active high, active low)
    • Gate control enabling (enables usage of external digital signal to enable the switching)
    • Sen (digital input selection for PWM enable)

A schematic block diagram of the inverter switching block is given in Figure 1 with corresponding switch arrangement and naming.

Input parameter configuration enables the user to assign gate drive inputs to any of the digital input pins (from 1 to 32). For example, if Phase A S1 is assigned to 1, the digital input pin 1 will be routed to the Phase A S1 switch gate drive. In addition, the gate_logic parameter selects either active high (High-level input voltage VIH turns on the switch), or active low (Low-level input voltage VIL turns on the switch) gate drive logic, depending on the user’s external controller design.

Model, when selected for Control parameter, enables the user to set the IGBTs gate drive signals directly from signal processing model. The input pin gates appears on the component and requires a vector input of six gate drive signals in the following order: [Phase A S1, Phase A S2, Phase B S1, Phase B S2, Phase C S1, Phase C S2]. When controlled from the model, logic is always active high.

Gate control enabling, when checked, enables using an external PWM enabling digital signal.

Figure 1. A schematic block diagram of a three-phase two level current source inverter block diagram with corresponding switch naming