Antiparallel thyristor leg
This section describes antiparallel thyristor legs
A block diagram and input parameters for anantiparallel thyristor leg are given in Table 1.
component | component dialog window | component parameters |
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Antiparallel thyristors |
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A schematic block diagram of the antiparallel thyristor leg is given in Figure 1 with corresponding thyristor arrangement and naming.
Digital inputs, when selected as control input option, enables the user to assign the gate drive inputs to any of the digital input pins (from 1 to 32). For example, if S1 is assigned to 1, the digital input pin 1 will be routed to the S1switch gate drive. In addition, thegate_logic parameter selects either active high(High-level input voltage VIHturns on the switch), or active low (Low-level input voltage VILturns on the switch )gate drive logic, depending on the user’s external controller design.
Model control, when selected for Control parameter, enables the user to set the thyristor gate drive signals directly from signal processing model. The input pin that appear on the top of the converter requires a vector input of two gate drive signals in the following order: [S1, S2]. When controlled from the model, logic is always active high.Digital Alias
If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.