This section describes three-phase to single-phase six pulse cycloconverter
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A block diagram and input parameters for a single
three-phase to single-phase cycloconverter are given in Table 1.
Table 1. A three-phase to single-phase cycloconverter component in the Schematic Editor core
library
component
component dialog window
component parameters
Three-phase to single-phase cycloconverter
Control source (Digital inputs/ Model)
Digital input pins for:
Phase A S1 (1..32)
Phase A S3 (1..32)
Phase B S1 (1..32)
Phase B S3 (1..32)
Phase C S1 (1..32)
Phase C S3 (1..32)
Phase A S4 (1..32)
Phase A S2 (1..32)
Phase B S4 (1..32)
Phase B S2 (1..32)
Phase C S4 (1..32)
Phase C S2 (1..32)
gate_logic (active high, active low)
_control_property (all high, all low)
Gate control enabling (enables usage of external digital signal to enable the
switching)
Sen (digital input selection for PWM enable)
Sen_logic (all high, all low)
Weight = 3
A schematic block diagram of a three-phase to single-phase cycloconverter block is
given in Figure 1 with corresponding thyristor
arrangement and naming.
Digital inputs, when selected as
icontrol input option, enables the user to assign gate drive inputs to any of the digital
input pins (from 1 to 32/64). For example, if Phase A S1 is assigned
to 1, the digital input pin 1 will be routed to the Phase A S1 switch
gate drive. In addition, the gate_logic parameter selects either
active high (High-level input voltage VIH turns on the
switch), or active low (Low-level input voltage VIL
turns on the switch) gate drive logic, depending on the user’s
external controller design.
Figure 1. A schematic block diagram of a three-phase to single-phase cycloconverter block
diagram with corresponding switch namingModel control, when selected for Control
parameter, enables the user to set the thyristor gate drive signals directly from signal
processing model. The input pin that appears on the top of the rectifier requires a vector
input of twelve gate drive signals in the following order: [Phase A S1, Phase A S2, Phase A
S3, Phase A S4, Phase B S1, Phase B S2, Phase B S3, Phase B S4,Phase C S1, Phase C S2, Phase C
S3, Phase C S4]. When controlled from the model, logic is always active high.