Three Phase Three Level Flying Capacitor Inverter

This section describes the three-phase three-level flying capacitor inverter component in Schematic Editor

A block diagram and input parameters for the inverter block are given in Table 1.

Table 1. A three-phase three-level flying capacitor inverter in the Schematic Editor core library
component component dialog window component parameters

Three phase three level flying capacitor inverter
  • General
    • Control(Digital inputs, Model)
    • Phase A S1 (1..32)
    • Phase A S2 (1..32)
    • Phase A S3 (1..32)
    • Phase A S4 (1..32)
    • Phase B S1 (1..32)
    • Phase B S2 (1..32)
    • Phase B S3 (1..32)
    • Phase B S4 (1..32)
    • Phase C S1 (1..32)
    • Phase C S2 (1..32)
    • Phase C S3 (1..32)
    • Phase C S4 (1..32)
    • gate_logic (active high, active low)
    • Gate control enabling (enables usage of external digital signal to enable the switching)
    • Sen (digital input selection for PWM enable)
    Weight = 3

A schematic block diagram of the inverter switching block is given in Figure 2 with its corresponding switch arrangement and naming.

Digital inputs, when selected as the Control parameter, enables assignment of gate drive inputs to any of the digital input pins (from 1 to 32). For example, if Phase A S1 is assigned to 1, the digital input pin 1 will be routed to the Phase A S1 switch gate drive. In addition, the gate_logic parameter selects either active high (High-level input voltage VIH turns on the switch), or active low (Low-level input voltage VIL turns on the switch) gate drive logic, depending on the external controller design under test.

Model, when selected as the Control parameter, enables IGBT gate drive signals to be set up directly from the signal processing model. The input pin gates appears on the component and requires a vector input of twelve gate drive signals in the following order: [Phase A S1, Phase A S2,…, Phase B S1, Phase B S2, … , Phase C S1, Phase C S2, ...]. When controlled from the model, logic is always active high.

Selecting Internal modulator as the Control parameter, enables use of the internal PWM modulator for driving the switches instead of the digital input pins. In this configuration, four additional component inputs will be present. The En input is used to enable/disable the internal PWM modulator, while InA, InB, and InC are used as a reference signal inputs for the corresponding converter legs. Each of the legs implements the modulation strategy shown in Figure 1.

Figure 1. The schematic diagram of an internal modulator for three-level flying capacitor leg

Gate control enabling, when checked, enables using an external PWM enabling digital signal.

Figure 2. A schematic block diagram of a three-phase three-level flying capacitor inverter block diagram with corresponding switch naming

Timing

When Enable delays is enabled, a turn on and turn off delay of the IGBTs will be included in the simulation. More information about this feature can be found in the dedicated switching delay section.

Digital Alias

If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.