Single-phase thyristor rectifier

This section describes single-phase thyristor rectifiers

A block diagram and input parameters for a single phase thyristor rectifier are given in Table 1.

Table 1. Single phase thyristor rectifier component in the Schematic Editor core library
component component dialog window component parameters

Single phase thyristor rectifiers

  • Control source (Digital inputs, Model)
  • Digital input pins for:
    • S1 (1..32)
    • S2 (1..32)
    • S3 (1..32)
    • S4 (1..32)
  • S1 logic (active high, active low)
  • S2 logic (active high, active low)
  • S3 logic (active high, active low)
  • S4 logic (active high, active low)
  • _control_property (all high, all low)
  • Switching enabled
  • Sen (digital input selection for PWM enable))
  • Sen_logic (active high, active low
Weight = 2

A schematic block diagram of the single phase thyristor rectifier block is given in Figure 1 with corresponding thyristor arrangement and naming.

Digital inputs, when selected as a control input option, enables the user to assign gate drive inputs to any of the digital input pins (from 1 to 32/64). For example, if S1 is assigned to 1, the digital input pin 1 will be routed to the S1switch gate drive. In addition, theS1 logic, S2 logic, S3 logic, and S4 logic parameters select either active high(High-level input voltage VIHturns on the switch), or active low(Low-level input voltage VILturns on the switch) gate drive logic, depending on the user’s external controller design.

Figure 1. The schematic block diagram of a single-phase thyristor rectifier block diagram, with corresponding switch naming
Model control, when selected for Control parameter, enables the user to set the thyristor gate drive signals directly from signal processing model. The input pin that appear on the top of the rectifier requires a vector input of four gate drive signals in the following order: [S1, S2, S3, S4]. When controlled from the model, logic is always active high.

PESB Optimization

The PESB Optimization option is available in certain converter models. When PESB Optimization is enabled, all converter's short circuit state space modes will be merged and treated as the same state space mode. For example, if one converter leg within the three phase converter is short circuited and PESB Optimization is enabled, all of the legs within the three phase converter will also be short circuited. This simplification for short circuit modeling can save a significant amount of matrix memory.

Digital Alias

If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.