HERIC converter

This section describes HERIC converter

A block diagram and input parameters for a converter block are given in Table 1.

Table 1. HERIC converter component in the Schematic Editor core library
component	component dialog window	component parameters
HERIC converter		General Control (Digital inputs, Model) AC Clamp (single, double) S1 (1..32(64)) S2 (1..32(64)) S3 (1..32(64)) S4 (1..32(64)) S5 (1..32(64)) S6 (1..32(64)) S7 (1..32(64)) - available if AC Clamp is double S8 (1..32(64)) - available if AC Clamp is double gate_logic (active high, active low) Gate control enabling (enables usage of external digital signal to enable the switching) Sen (digital input selection for PWM enable) Advanced PESB optimization Weight = 2

A schematic block diagram of the single AC clamp HERIC converter and double AC clamp HERIC converter switching block with corresponding switch arrangement and naming are given in Figure 1 and Figure 2, respectively.

Digital inputs, when selected as the Control parameter, enables you to assign gate drive inputs to any of the digital input pins (from 1 to 32(64)). For example, if S1 is assigned to 1, the digital input pin 1 will be routed to the S1 switch gate drive. In addition, the gate_logic parameter is set to either active high (i.e. high-level input voltage VIH, which turns on the switch), or active low (i.e. low-level input voltage VIL, which turns on the switch). The gate drive logic depends on your external controller design.

Figure 1. A schematic block diagram of a HERIC converter block (single AC clamp) with corresponding switch naming

Figure 2. A schematic block diagram of a HERIC converter block (double AC clamp) with corresponding switch naming

Model, when selected as the Control parameter, enables you to set the IGBTs gate drive signals directly from the signal processing model. The input pin gates appears on the component, which requires a vector input of six or eight gate drive signals depending on the AC clamp type. If AC clamp is single, the gate drive signals must be in the following order: [S1, S2, S3, S4, S5, S6]. If AC clamp is double, the gate drive signals must be in the following order: [S1, S2, S3, S4, S5, S6, S7, S8]. When controlled from the model, the logic is always set to active high.

PESB Optimization

The PESB Optimization option is available in certain converter models. When PESB Optimization is enabled, all converter's short circuit state space modes will be merged and treated as the same state space mode. For example, if one converter leg within the three phase converter is short circuited and PESB Optimization is enabled, all of the legs within the three phase converter will also be short circuited. This simplification for short circuit modeling can save a significant amount of matrix memory.

Digital Alias

If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.