Active Full Wave Rectifier

This section describes Active Full Wave Rectifier

A block diagram and input parameters for Active Full Wave Rectifier are given in Table 1.

Table 1. Active Full Wave Rectifier component in the Schematic Editor core library
component component dialog window component parameters

Active Full Wave Rectifier

  • General
    • Control (Digital inputs, Internal modulator, Model)
    • S1 (digital input selection for switch S1)
    • S2 (digital input selection for switch S2)
    • S1_logic (active high, active low)
    • S2_logic (active high, active low)
    • _control_property (all high, all low)
    • PWM enabling (enables usage of external digital signal to enable the switching)
    • Sen (digital input selection for PWM enable))
    • Sen_logic (active high, active low
Weight = 1

A schematic block diagram of the Active Full Wave Rectifier is given in Figure 1, with corresponding switch arrangement and naming.

Digital inputs, when selected for Control parameter, enables the user to assign gate drive inputs to any of the digital input pins (from 1 to 32(64)). For example, if S1 is assigned to 1, the digital input pin 1 will be routed to theS1switch gate drive. In addition, the gate_logic parameter selects either active high(High-level input voltage VIH turns on the switch), or active low(Low-level input voltage VIL turns on the switch) gate drive logic, depending on the user’s external controller design.

Figure 1. A schematic block diagram of an Active Full Wave Rectifier with corresponding switch naming

Internal modulator, when selected for Control parameter, enables the user to use internal PWM modulator for driving S1 and S2 switches instead of digital input pins. In this configuration, two additional component inputs will be present. En input is used as enable/disable and In1 and In2are used as referent signals inputs for internal PWM modulators.

Model, when selected for Control parameter, enables the user to set the IGBTs gate drive signals directly from signal processing model. The input pin gates appears on the component. It is 2 element vector input, where first value (index 0) controls S1 gate and second value (index 1) controls S2 gate. When controlled from the model, logic is always active high.

PWM enabling, when checked, enables using an external PWM enabling digital signal.

PESB Optimization

The PESB Optimization option is available in certain converter models. When PESB Optimization is enabled, all converter's short circuit state space modes will be merged and treated as the same state space mode. For example, if one converter leg within the three phase converter is short circuited and PESB Optimization is enabled, all of the legs within the three phase converter will also be short circuited. This simplification for short circuit modeling can save a significant amount of matrix memory.

Digital Alias

If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.