Model partitioning

This section describes the general motivation and gives some practical guidelines for model partitioning.

The main goal of model partitioning is to speed up the simulation of large and complex models by enabling parallel computing. Model partitioning is categorized by the part of the model being partitioned and its scope.

There are two key parts of a Schematic Editor model that can be partitioned:
  • Signal processing partitioning - partitioning the signal processing part of the scheme in order to compute it in multiple general purpose processors (GPU).
  • Electric circuit partitioning - partitioning the electrical part of the circuit in order to compute it on multiple, dedicated FPGA cores or multiple FPGAs.
Based on the scope of the partitioning, two other groups can be distinguished:
  • Core partitioning - partitioning the scheme in multiple cores/GPUs of the same HIL device.
  • Device partitioning - partitioning the scheme in multiple HIL devices.

For further information about partitioning the electric circuit part please refer to Electric circuit partitioning. Example of partitioning the signal processing part of the scheme is presented in Signal processing scheme partitioning.