Model partitioning

This section describes the general motivation and gives some practical guidelines for model partitioning.

Note: An interactive overview of the concepts and/or capabilities described here are available as part of the HIL Specialist 2.0 certification program on HIL Academy, as well as in the video Knowledgebase.

The main goal of model partitioning is to speed up the simulation of large and complex models by enabling parallel computing, thus dividing complex models into smaller segments, allowing them to fit within the fixed time-step requirements of real-time simulations. Model partitioning is categorized by the part of the model being partitioned and its scope.

In TyphoonSim, fixed time-step constraint is absent. Offline (non-real-time) simulators, like TyphoonSim, use variable simulation step in their simulations, so the real-time constraints are not a concern. As a result, model partitioning is not required for offline simulations because there is no need to split the model to improve computational performance within a fixed time frame.

Note: All upcoming descriptions are related only to real-time/VHIL simulation.

There are two key parts of a Schematic Editor model that can be partitioned:

Signal processing partitioning - partitioning the signal processing part of the scheme in order to compute it in multiple general purpose processors (GPU).
Electric circuit partitioning - partitioning the electrical part of the circuit in order to compute it on multiple, dedicated FPGA cores or multiple FPGAs.

Based on the scope of the partitioning, two other groups can be distinguished:

Core partitioning - partitioning the scheme in multiple cores/GPUs of the same HIL device.
Device partitioning - partitioning the scheme in multiple HIL devices.

Table 1. Classification of model partitioning components
Type of partitioning\Partitioning scope	Core partitioning	Device partitioning
Signal processing	CPU Marker CPU Transition	Signal Device Marker Device Transition
Electric circuit	Core Marker Single Phase Core Coupling Three Phase Core Coupling Four Phase Core Coupling Five Phase Core Coupling Single Phase TLM Core Coupling Three Phase TLM Core Coupling component Four Phase TLM Core Coupling component Single Phase Bergeron Model Three Phase Bergeron Model	Device Marker Single Phase Device Coupling Three Phase Device Coupling Four Phase Device Coupling Single Phase TLM Device Coupling Three Phase TLM Device Coupling component Four Phase TLM Device Coupling component

For further information about partitioning the electric circuit part please refer to Electric circuit partitioning. Example of partitioning the signal processing part of the scheme is presented in Signal processing scheme partitioning.