Electric circuit partitioning

This section describes the general motivation and gives some practical guidelines for electric circuit partitioning.

Motivation for electric circuit partitioning is to enable parallel computing of complex power electronics and power system models that usually contain large number of switches. An example of a two level back to back converter is used to illustrate the benefits.

Converters are modeled using ideal switches, where a combination of a controllable switch (IGBT) and an anti-parallel diode are represented as one switch. Two level back to back converter consists of two three-phase two-level converters, each of them contains six switches.

Each switch permutation is represented by a linear time-invariant (LTI) state space matrix. For the circuit presented, that contains 12 switches, number of permutation is 212 = 4096. In this case, 4096 state space matrices have to be stored. The size of memory space required to store the matrices rises exponentially as a function of number of switches.

If the circuit is split in two circuits, where each of them are executed on separate processors, or separate cores of a same processor, than the overall number of switch permutations per core is 26 = 64, overall number of matrices to be stored for both circuits is 2x64 = 128. Which is significantly less than 4096.

On other side, the time needed to simulate the circuit depends on the size and density of the state space matrices. If the full circuit is split, the matrices per core will be smaller, hence faster simulation rates can be achieved.

Figure 1: Two-level three-phase back-to-back converter

For further information abaout circuit partitioning, please refere to following pages:

Circuit partitioning components

Coupling component placement and parametrization - Ideal Transformer based couplings

Coupling component placement and parametrization - TLM based couplings

Multi-HIL specific circuit partitioning