Electrical domain modeling principles and constraints

This section describes electrical domain modeling principles and constraints.

This chapter introduces basic principles for electrical domain modeling and defines constraints in terms of electrical circuit size and complexity. Real-time emulation, in contrast to off-line simulation, imposes rigid timing limitations due to the fact that the model response calculation must be finished within the pre-defined simulation step. To achieve very short simulation steps (at a 1 ┬Ás level), response computation of complex models has to be parallelized. With this in mind, Typhoon HIL introduced a dedicated multi-core processor architecture implemented in FPGA fabric. Consequently, in order to understand the fundamentals behind modeling principles and constraints thereof, it is important to understand the FPGA solver processor architecture.

This chapter includes the detailed explanations of the following topics which allow you to gain full understanding of electrical modeling principles and constraints stemming from them:

FPGA solver basics

Loop-back Latency

Switch models

Irregular Model Example

Topological Conflicts

Electric circuit partitioning

GDS oversampling