Split-Source Inverter

A block diagram and input parameters for an inverter block are given in Table 1

Table 1. A Split-Source inverter component in the Schematic Editor core library

component	component dialog window	component parameters
Split-Source inverter		General Control (Digital inputs, Internal modulator, Model) Phase A S1 (1..32(64)) Phase A S2 (1..32(64)) Phase B S1 (1..32(64)) Phase B S2 (1..32(64)) Phase C S1 (1..32(64)) Phase C S2 (1..32(64)) gate_logic (active high, active low) Gate control enabling (enables usage of external digital signal to enable the switching) Sen (digital input selection for PWM enable) Advanced PESB optimization Snubber resistance Weight = 3

A schematic block diagram of the inverter switching block is given in Figure 1 with corresponding switch arrangement and naming.

Digital inputs, when selected for Control parameter, enables the user to assign gate drive inputs to any of the digital input pins (from 1 to 32(64)). For example, if Phase A S1 is assigned to 1, the digital input pin 1 will be routed to the Phase A S1 switch gate drive. In addition, the gate_logic parameter selects either active high (High-level input voltage VIH turns on the switch), or active low (Low-level input voltage VIL turns on the switch) gate drive logic, depending on the user’s external controller design.

Internal modulator, when selected for Control parameter, enables the user to use internal PWM modulator for driving Phase A S1, Phase A S2, Phase B S1, Phase B S2, Phase C S1 and Phase C S2 switches instead of digital input pins. In this configuration, four additional component inputs will be present. En input is used as enable/disable and InA, InBand InC are used as referent signal inputs for internal PWM modulator. If Operation mode is Variable carrier frequency, one additional compontent input will be present, freq. This input can be used to control PWM carrier frequency.

Model, when selected for Control parameter, enables the user to set the IGBTs gate drive signals directly from signal processing model. The input pin gates appears on the component and requires a vector input of six gate drive signals in the following order: [Phase A S1, Phase A S2, Phase B S1, Phase B S2, Phase C S1 and Phase C S2]. When controlled from the model, logic is always active high.

PESB Optimization

When PESB Optimization is enabled, all converter's short circuit state space modes will be merged and treated as the same state space mode. For example, if one converter leg within the three phase converter is short circuited and PESB Optimization is enabled, all of the legs within the three phase converter will also be short circuited. This simplification for short circuit modeling can save a significant amount of matrix memory.

Snubber resistance

Use to specify snubbers resistance.

Digital Alias

If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.