ANPC Flying Capacitor Inverter 7 Level Leg

Description of the seven-level ANPC flying capacitor inverter component in Schematic Editor Library

A block diagram and input parameters for the seven-level ANPC flying capacitor inverter are given in Table 1.

Table 1. ANPC flying capacitor inverter 7 level leg block in the HIL Toolbox
component component dialog window component parameters

ANPC flying capacitor inverter 7 level leg

  • General
    • Control (Digital inputs, Model)
    • Gate control enabling (allows use of an external digital signal to enable switching)
    • Sen (digital input selection for PWM enable)
    • Sen_logic (active high, active low)
  • Input Stage
    • S1 (digital input selection for switch S1)
    • S2 (digital input selection for switch S2)
    • S3 (digital input selection for switch S3)
    • S4 (digital input selection for switch S4)
  • Flying Cap Stage
    • S5 (digital input selection for switch S5)
    • S6 (digital input selection for switch S6)
    • S7 (digital input selection for switch S7)
    • S8 (digital input selection for switch S8)
    • S9 (digital input selection for switch S9)
    • S10 (digital input selection for switch S10)
    Weight = 2
Figure 1 shows a schematic block diagram of the inverter switching block with corresponding switch arrangement and naming.

Digital inputs, when selected as the Control parameter, enables you to assign gate drive inputs to any of the digital input pins (from 1 to 32). For example, if S1 is assigned to 1, the digital input pin 1 will be routed to the S1 switch gate drive. In addition, the S1_logic parameter is set to either active high (i.e. high-level input voltage VIH turns on the switch) or active low (i.e. low-level input voltage VIL turns on the switch). The gate drive logic depends on your external controller design.

Model, when selected as the Control parameter, enables you to set the IGBT gate drive signal directly from the signal processing model. The input pin gate appears on the component. It is a vector input, of ten gate drive signals in the following order: [S1, S2, … , S9, S10]. When controlled from the model, the logic is always set to active high.

Gate control enabling, when checked, allows PWM enabling from an external digital signal.

Figure 1. A schematic block diagram of the seven-level ANPC flying capacitor inverter block diagram with corresponding switch naming

Digital Alias

If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.