Three Level Flying Capacitor Inverter Leg

Description of the three-level flying capacitor leg component in Schematic Editor

A block diagram and input parameters for the three level flying capacitor leg are given in Table 1.

Table 1. Three level flying capacitor leg in the Schematic Editor core library
component component dialog window component properties

Three Level Flying Capacitor Leg

  • General
    • Control(Digital inputs, Model)
    • FSM Selection(Reduced, Full)
    • S_1 (digital input selection for switch S1)
    • S_2 (digital input selection for switch S2)
    • S_3 (digital input selection for switch S3)
    • S_4 (digital input selection for switch S4)
    • PWM enabling (enables usage of external digital signal to enable the switching)
    • Sen (digital input selection for PWM enable)
Figure 1. A schematic block diagram of a Three Level Flying Capacitor Leg block diagram with its corresponding switch naming

Digital inputs, when selected as the Control parameter, enables assignment of gate drive inputs to any of the digital input pins (from 1 to 32(64)). For example, if S_1 is set to 1, the digital input pin 1 will be routed to the S1 switch gate. In addition, the S_1_logic parameter selects either active high (High-level input voltage VIH turns on the switch), or active low (Low-level input voltage VIL turns on the switch) gate logic, depending on the external controller design under test.

Selecting Internal modulator as the Control parameter, enables use of the internal PWM modulator for driving the switches instead of the digital input pins. In this configuration, two additional component inputs will be present. The En input is used to enable/disable the internal PWM modulator, while In is used as a reference signal input. Figure 2 shows the schematic diagram of the PWM modulation strategy. The PWM Modulator1 uses the triangular carrier with signal range 0 to 1, while the PWM Modulator2 uses the triangular carrier with signal range -1 to 0. The red signal is the top output of a modulator, while the green signal is the bottom one.

Figure 2. The schematic diagram of an internal modulator for three-level flying capacitor leg

Model, when selected as the Control parameter, enables IGBT gate drive signals to be set directly from the signal processing model. The input pin gates appears on the component and requires a vector input of four gate drive signals in the following order: [S_1, S_2, S_3, S_4]. When controlled from the model, logic is always active high.

FSM Selection selects if the model should run for all states or should only run for a reduced number of states.

PWM enabling, when checked, enables using an external PWM enabling digital signal.


When Enable delays is enabled, the turn on and turn off delay of the IGBTs will be included in the simulation. More information about this feature can be found on the dedicated section switching delay.

PESB Optimization

The PESB Optimization option is available in certain converter models. When PESB Optimization is enabled, all converter's short circuit state space modes will be merged and treated as the same state space mode. For example, if one converter leg within the three phase converter is short circuited and PESB Optimization is enabled, all of the legs within the three phase converter will also be short circuited. This simplification for short circuit modeling can save a significant amount of matrix memory.

Digital Alias

If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.