Single-phase two level H5 inverter

This section describes single-phase two level H5 inverter

A block diagram and input parameters for the H5 inverter block are given in Table 1.

Table 1. A single-phase two-level H5 inverter component in the Schematic Editor core library
component component dialog window component parameters

Single phase two level H5 inverter

  • General
    • Control(Digital inputs, Model)
    • S1 (1..32)
    • S2 (1..32)
    • S3 (1..32)
    • S4 (1..32)
    • S5 (1..32)
    • gate_logic (active high, active low)
    • Gate control enabling (enables usage of external digital signal to enable the switching)
    • Sen (digital input selection for PWM enable)
    Weight =1

A schematic block diagram of the inverter switching block is given in Figure 1 with corresponding switch arrangement and naming.

Figure 1. A schematic block diagram of a single-phase two level H5 inverter block diagram with corresponding switch naming.

Digital inputs, when selected for Control parameter, enables the user to assign gate drive inputs to any of the digital input pins (from 1 to 32).For example, if S1 is assigned to 1, the digital input pin 1 will be routed to the S1 switch gate drive. In addition, the gate_logic parameter selects either active high(High-level input voltage VIHturns on the switch), or active low(Low-level input voltage VILturns on the switch) gate drive logic, depending on the user’s external controller design.

Model, when selected for Control parameter, enables the user to set the IGBTs gate drive signals directly from signal processing model. The input pin gates appears on the component and requires a vector input of five gate drive signals in the following order: [S1, S2, S3, S4, S5]. When controlled from the model, logic is always active high.

Gate control enabling, when checked, enables using an external PWM enabling digital signal.

PESB Optimization

The PESB Optimization option is available in certain converter models. When PESB Optimization is enabled, all converter's short circuit state space modes will be merged and treated as the same state space mode. For example, if one converter leg within the three phase converter is short circuited and PESB Optimization is enabled, all of the legs within the three phase converter will also be short circuited. This simplification for short circuit modeling can save a significant amount of matrix memory.

Digital Alias

If a converter is controlled by digital inputs, an alias for every digital input used by the converter will be created. Digital input aliases will be available under the Digital inputs list alongside existing Digital input signals. The alias will be shown as Converter_name.Switch_name, where Converter_name is name of the converter component and Switch_name is name of the controllable switch in the converter.