Sample and Hold

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Description

The Sample and Hold component samples an input signal each time a trigger event is detected. The sampled value is held until the next time the component is triggered. The Sample and Hold component can be configured to trigger on rising edges, falling edges, both rising and falling edges, or on level. When configured to trigger on level, a relational operator and threshold may be set to determine when sampling occurs. In this mode, sampling will occur continuously while the level criterion is satisfied. The Edge Detection component detects rising, falling or both rising and falling edges of the input signal.

The Sample and Hold component is realized as a composite component comprised of Edge Detection, Unit Delay, and Signal Switch components, as represented in Figure 2.

The output value of the Sample and Hold component can only store a single value or array in memory at any given time.

Ports

• Signal input terminal
  • Supported types: uint, int, and real.
  • Vector support: yes.

• Trigger input terminal
  • Supported types: uint, int, and real.
  • Vector support: yes.
• Output terminal
  • Supported types: uint, int, and real.
    • The output type is inherited from the input signal.
  • Vector support: yes.
    • The vector length is inherited from the input signal.

Properties

• Trigger on
  • Select the preferred trigger feature. Triggering can be configured to occur at rising and/or falling edges or on level conditions.
• Relational operator
  • Level only: specifies the inequality with which to evaluate the incoming signal. Configures sampling to trigger when the trigger input is greater than, greater than or equal to, or not equal to some target threshold.
• Threshold for detection
  • Level only: sets the threshold for triggering when the Relational operator is configured to trigger on level.
• Initial value
  • Configures the initial output value of the Sample and Hold component. This value will be output until a new trigger event is detected.

• Execution rate
  • Type in the desired signal processing execution rate. This value must be compatible with other signal processing components of the same circuit: the value must be a multiple of the fastest execution rate in the circuit. There can be up to four different execution rates, but they must all be multiple of the basic simulation timestep. To specify the execution rate, you can use either decimal (e.g. 0.001) or exponential values (e.g. 1e-3) in seconds. Alternatively, you can type in ‘inherit’ in which case the component will be assigned execution rate based on the execution rate of the components it is receiving input from.