Model Settings

This section describes the Model Settings dialog in Schematic Editor and its options.

Table 1. Hardware settings
Option name	Description
Device	Specifies for which device the schematic is intended. Currently supported device settings include HIL402, HIL101, HIL404, HIL602+, HIL604, HIL506, HIL606, and VHIL+.
Configuration id	Specifies the configuration ID for the selected device. Available configurations are determined by the selected Device.
Device table	Shows a table with details for the selected device. For more information, see Device Configuration Table.
Autodetect settings	Choose device and configuration ID based on the connected device.
Limit device analog outputs to +/- 5 V	By checking this option, the analog outputs are limited to +/- 5 V. Otherwise, analog outputs are in range +/- 10 V.
Reset analog outputs on simulation stop	By checking this option, the analog outputs can be forced to reset to a pre-determined value when the simulation stops. Otherwise, outputs will maintain the last recorded value at simulation stop.
Reset analog outputs value	Specifies the reset values when Reset analog outputs on simulation stop is checked. Available values are Offset Value and Zero Volts.
Reset digital outputs on simulation stop	By checking this option, the digital outputs can be forced to reset to 0 when the simulation stops. Otherwise, outputs will maintain the last recorded value at simulation stop.

Note: VHIL+ is a unique Virtual HIL configuration that does not correspond to a physical HIL device. For more information, please refer to the Device Configuration Table documentation.

Table 2. Circuit Solver settings
Option name	Description
Discretization method	Choose the discretization method for state space equations of the model.
Simulation step	If the simulation step is set to 'auto', the model will be simulated with the smallest acheivable simulation time step from the predefined list.
Simulation rate scaling	The discretization step is calculated as simulation step/scaling.
Calculation method	There are two available algorithms for state space matrix calculation of the model. By default, systematic elimination is used. In some extraordinary cases, constraint matrix algorithm is required.
Enhance stability	Cancels out the positive poles of the system due to numerical calculation errors, which ensures the stability of long simulation runs.
Enable GDS oversampling	Enables high resolution sampling of converter control inputs (gate drive signals). Recommended for switching frequencies exceeding 4kHz. When enabled, it adds one additional simulation step of latency measured from digital inputs to analog outputs.
Enable coupling stability analysis	Enable core coupling stability analysis.
Enable VHIL analog/digital IO loopback	Enable use of analog and digital IO on Virtual HIL. The analog/digital IO is looped back to the appropriate input.

Table 3. Signal processing settings
Option name	Description
Place code section in	Target memory selection for the code program sections.
Place data section in	Target memory selection for the data program sections.
Compiler optimization level	Choose the level of optimization for the user CPU. If you select to compile a SP (Signal Processing) model with a changed optimization level, it is highly recommended to manually restart the HIL before loading the model.
Real type mapping	Choose the real type precision for the user CPU.
CPU mapping option	Defines the CPU partitioning algorithm mode of operation: default - CPU marker components apply to the connected Signal Processing component group. Component groups with no CPU markers are mapped to the CPU core 0. CPU Transition components are used as separators for CPU partitioning. execution rate based - This mode allows model mapping on multiple CPU cores without the need to use CPU transition and CPU marker components. CPU partition is done based on the execution rates present in the model. This way, rate transition components can also serve as separators for CPU partitioning. When CPU markers are used, they apply to the whole connected execution rate in the model. When CPU markers are not used, the compiler automatically maps execution rates to the available CPU cores.
Execution rate 1	Define the fast execution rate for the system signal.
Execution rate 2	Define the slow execution rate for the system signal.
Compiler optimization level	Choose the level of optimization for the system CPU.
Tunable parameters	Global switch for the behavior of tunable parameters in supported components: component defined - With this setting each component can be individually configured to use tunable parameters in their respective property windows. off - Disables tunable parameters entirely regardless of the component setting. on - Enables tunable parameters for all components in the model that support it regardless of the component settings.
Compiler type	Choose what compiler to use when compiling the Signal Processing part of the model. Available options are: C compiler C++ compiler

Table 4. External tools
Option name	Description
PSIM install dir	Defines path to the PSIM installation that will be used for the Model Converter functionality.

Table 5. C Code Export
Option name	Description
Export directory	Define the directory where C code will be exported.
int	Define type mapping for int Typhoon type. By default int is mapped to int C type.
uint	Define type mapping for uint Typhoon type. By default uint is mapped to unsigned int C type.
real	Define type mapping for real Typhoon type. By default real is mapped to double C type.

Table 6. Diagnostics
Option name	Description
Report inconsistent usage of terminal feedthrough as	You can select in which way errors related to terminals' feedthrough in C functions will be reported. When a warning is selected, compilation of the model will continue and even though there is a possibility that your model will work on a HIL device, it also may lead to incorrect results. When an error is selected, compilation will stop and you will have to make corrections to your code.

Note: Diagnostics tab has been added since the 2023.3 software release. New mechanisms for detection of incorrectly written C code have been added and it may cause previously undetected errors to now be reported.

More rules on how to write C code can be found in the Rules for writing C code section.