Implementation information

Basic information about the implementation of communication protocols in the Typhoon HIL toolchain

Real-time only: This document is valid only for real-time/VHIL simulation.

The Typhoon HIL toolchain features three different methods for implementing communication protocols: as an embedded Linux application; as a bare-metal application; or as a protocol implemented in the hardware. The requirements of the protocol defines the implementation:

Naturally, if a protocol has higher speed/determinism requirements, the needed hardware resources will also increase. For protocols that require a hardware implementation, additional space on the FPGA must be reserved to implement the required IP Cores. Bare-metal protocols require a separate processor core for each application, while embedded Linux protocols have the most relaxed requirements, so multiple protocols can run on a single Linux processor core in parallel.

Only certain HIL devices and certain firmware configurations support one or more protocols that require a hardware implementation. This is defined in the Device Configuration Table.

Bare-metal communication protocols are executed on a dedicated processing cores called COMM CPU (short for Communication CPU). 4th generation HIL devices (HIL101, HIL404, HIL506, and HIL606) have 2 COMM CPU cores, while all previous generations have only 1 COMM CPU core. In other words, on a 4th generation HIL device, 2 bare-metal communication protocols can run in parallel, and on the other generations, just one.

The embedded Linux CPU core does not have a limitation on how many communication protocols can run simultaneously at the same time. However, running too many embedded Linux protocols in parallel may cause some degradation in model performance due to excessive CPU utilization.