# Loop-back Latency

This section describes the overall loop-back latency with focus on digital input to analog output latency.

Overall loop-back latency from digital input to analog output can be in range of {Ts+640ns, 4*Ts+640ns } for single core models, where Ts is the simulation step. Latency depends on the sampling uncertainty, hardware characteristics, software settings and model itself. In this section the minimal and maximal loop-back latency cases are presented and the delays within the system are explained. Hints how to reduce the latency are given.

In Figure 1 a general case for latency is presented. The most significant loop-back latency is from digital inputs to digital outputs. It consists of three different causes :
• Sampling uncertainty - digital inputs are sampled within the simulation cycle, change of the digital input signal can occur anywhere during that time, but it is going to be applied in next simulation cycle. In worst case scenario change of the digital inputs occur in the beginning of the simulation cycle resulting in larger latency; in best case scenario the switching event occurs close to the end of the simulation cycle, resulting in smaller latency.
• Software/model related - it is always a integer multiply of the simulation step, ranging from 1 simulation step to several
• Hardware latency - is a fixed delay time, it can be different among the device types. Most significant delays are digital output delay (~250ns) and analog output delay (~640ns).

Digital output signal presented in Figure 1 is a direct feed through of a digital input, there for it's latency is coming only from sampling uncertainty and delay of digital output stage. This case is will not be described further.

Maximal sampling latency and software/model dependent latency depend on the simulation step. It is obvious that reduction of the simulation step is going to result in smaller latency thus this is not going to be analysed or described further.

## Minimal Loop Back Latency

As noted in description of latency causes in general, only software/model related latency can be minimized (for given simulation step). In this section a case of minimal latency is presented. Model used during the measurements and relevant settings are presented in Figure 2.

System setup:
• Gate drive signals connected to digital inputs 1 and 2 for top and bottom switches respectively.
• Inductor current L1 set at analog output 1 - it is important to note that L1 was used directly, and not Ia1 in order to get minimal latency; it is possible to use Ia1 as well by setting Exact measurement option to True.
• GDS oversampling disabled - it adds an additional simulation cycle of latency when enabled.
• Loop-back latency measured from event on digital input 1 to response on analog output 1.
Results obtained during the test are shown in Figure 3. It can be seen that there are three major components of the overall latency:
• Tevent - sampling uncertainty described previously.
• Tsc - state calculation time which is equal to the software defined simulation step.
• Tao - latency of the analog output.
Overall latency is sum of these three, due to the sampling uncertainty, it is within the following range:

${T}_{latency}\in \left({T}_{s}+{T}_{ao},2*{T}_{s}+{T}_{ao}\right)$

## Maximal loop-back latency case

In this section a case of maximal loop-back latency is presented. Model used during the test is the same as for the minimal loop-back latency test case while the software settings and some component options are different. Relevant changes in software settings are highlighted in Figure 4.

System setup:
• Gate drive signals connected to digital inputs 1 and 2 for top and bottom switches respectively.
• Current measurement Ia1 set at analog output 1
• Current measurement parameter Exact measurement is set to False.
• GDS oversampling enabled - it adds an additional simulation cycle of latency
• Loop-back latency measured from event on digital input 1 to response on analog output 1.
Results obtained during the test are shown in Figure 5. It can be seen that there are three major components of the overall latency:
• Tevent - sampling uncertainty described previously.
• Tsc - state calculation time, equal to the software defined simulation step.
• Tcmp - compensation time, equal to the software defined simulation step; applies only if oversampling is enabled
• Toc - output calculation time, equal to the software defined simulation step; applies only if Exact measurementoption in measurement properties is enabled.
• Tao - latency of the analog output.
Overall latency is sum of these three, due to the sampling uncertainty, it is within the following range:

${T}_{latency}\in \left(3*{T}_{s}+{T}_{ao},4*{T}_{s}+{T}_{ao}\right)$