+3 votes

Best answer

ZVS and switch-node ringing are typically closely associated with MOSFET output capacitance - C_{oss}. In modern SiC MOSFET devices, values of this capacitance is typically in range of 10s or 100s of pF.

Let us first consider the ZVS simulation for a two-level inverter leg, where output capacitance values for the MOSFETs are 100 pF. As an example, we can consider that the output current of the leg can be considered constant: *I _{leg}*=10 A. Lastly, let's consider that the DC voltage is

Similar observation can be made with regards to switch-node ringing. If we consider that the ringing is caused by oscillation which involves the C_{oss} and a non-parasitic inductance L=5uH, we can calculate the expected resonant frequency as fr=1/(2*pi*sqrt(L*C_{oss}))≈7.1MHz. Once again we conclude that we would need a time step shorter than 15 ns in order to properly simulate this, which is hardly achievable in real time.

We can conclude that it is not possible to simulate the parasitics-related phenomena in a real-time simulation. For a well-designed converter, these effects should not affect the control performance, meaning that the model without these effect should be sufficient for control testing.

Parasitics-related phenomena can be considered a hardware design concern. For this purpose, offline simulation with variable time step shall be used. Typhoon HIL provides this capability through **TyphoonSim**.

+1 vote

Unfortunately, simulating parasitics is not practically feasible to be determined on real-time simulation platforms simply because the simulation needs to be very fast to simulate such dynamics, which will not be currently possible with existing FPGA's. However, simulating losses can be efficiently done in Typhoon HIL.