IO Timing

Sample rates and timing details for HIL 4/6 Series devices.

Sample Rates

Table 1. HIL402, HIL602+, and HIL604 IO sample/update rates
IO class Sample/Update rate Comment
Digital input 160 MSPS All digital inputs are sampled simultaneously.
Digital output Up to 160 MSPS All digital outputs are updated simultaneously.
Analog input 1/t1 All analog inputs are sampled simultaneously. Minimum sample time is 1μs
Analog output 1/t1 All analog outputs are updated simultaneously.
Table 2. HIL404 and HIL606 IO sample/update rates
IO class Sample/Update rate Comment
Digital input 280 MSPS All digital inputs are sampled simultaneously.
Digital output Up to 280 MSPS All digital outputs are updated simultaneously.
Analog input 1/t1 All analog inputs are sampled simultaneously. Minimum sample time is 1μs
Analog output 1/t1 All analog outputs are updated simultaneously.

IO Timing Details

All analog IOs are updated/sampled in sync with the simulation step (t1), which is software defined. To improve the PWM sampling resolution, digital inputs actually are sampled at a higher rate (t2), independent of the simulation time step value. Similarly, digital outputs are updated at a higher t2 rate. For exact t2 value check the tables above. For overall expected loop-back latency please consult Loop-back Latency.

Figure 1. IO timing diagram
Table 3. Key Timing Parameters
Symbol Parameter Value
t1 Simulation step Software defined
t2 Digital input sampling time Device specific
Table 4. Output delays
IO class HIL402, HIL602+, and HIL604 HIL404 and HIL606
Digital output (Tdo) 250 ns 150 ns
Analog output (Tao) 640 ns 340 ns